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硅基毫米波雷达芯片研究现状与发展

贾海昆 池保勇

引用本文: 贾海昆, 池保勇. 硅基毫米波雷达芯片研究现状与发展[J]. 电子与信息学报, 2020, 42(1): 173-190. doi: 10.11999/JEIT190666 shu
Citation:  Haikun JIA, Baoyong CHI. The Status and Trends of Silicon-based Millimeter-wave Radar SoCs[J]. Journal of Electronics and Information Technology, 2020, 42(1): 173-190. doi: 10.11999/JEIT190666 shu

硅基毫米波雷达芯片研究现状与发展

    作者简介: 贾海昆: 男,1987年生,助理教授,研究方向为毫米波集成电路设计;
    池保勇: 男,1976年生,教授,研究方向为射频与毫米波集成电路设计
    通讯作者: 池保勇,chibylxc@tsinghua.edu.cn
  • 基金项目: 北京市科技计划(Z191100007519005)

摘要: 毫米波雷达具备全天候复杂环境下的工作能力,在汽车雷达、智能机器人等方面有广泛的应用。同时,随着半导体技术的快速发展,硅基工艺晶体管的截止频率提升,硅基毫米波雷达成为研究热点,大量的工作从系统设计、电路设计等方面提高毫米波雷达的性能。该文从系统和核心电路等方面对硅基毫米波雷达芯片的研究现状和发展趋势进行综述。

English

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  • 图 1  毫米波汽车雷达和谷歌Soli项目[14]

    图 2  毫米波雷达系统基本结构

    图 3  FMCW雷达探测静止目标和运动目标的原理示意图

    图 4  基本FMCW毫米波雷达收发机前端芯片结构图

    图 5  文献[34]中基于DSM小数型锁相环的FMCW信号发生器

    图 6  当锁相环建立时间过快时的输出FMCW频率波形

    图 7  全数字锁相环用于毫米波FMCW信号产生[37]

    图 8  合成型功率放大器

    图 9  4种4阶匹配网络[66]

    图 10  4种4阶匹配网络的频率响应对比[66]

    图 11  基于变压器耦合谐振腔的特性[67]

    图 12  理想两单元相控阵不同波束指向的雷达方向图

    图 13  片上传输线与键合线协同设计以提高其带宽[81]

    图 14  工作在60 GHz的键合线天线,增益为4 dBi[80]

    图 15  文献[82]倒封装

    图 16  封装天线示意图[84]

    图 17  在封装中集成了2×2的接收天线阵列以及1×2的发射天线阵列[13]

    图 18  MIMO天线阵列配置示意图

    图 19  2维MIMO天线阵列配置示意图

    图 20  两点调制基本原理[39]

    图 21  采用LMS相关算法校准高通支路与低通支路的匹配[39]

    表 1  FMCW信号发生器性能汇总

    文献编号[5][27][28][33][34][37][42][43]
    工艺65 nm CMOS,65 nm CMOS,65 nm CMOS,90 nm CMOS,65 nm CMOS,65 nm CMOS,65 nm CMOS,40 nm CMOS,
    结构DSM小数环DSM小数环DSM小数环DDFS整数环DSM小数环全数字小数环混合信号小数环CTDSM小数环
    频率(GHz)76.076~81777776608337
    扫频带宽(GHz)0.7000.5001.9300.6140.7001.2201.5000.500
    RMS频差(kHz)64±961674>1000<73117<180820
    功耗(mW)73.0320.0N/A101.051.448.0152.068.0
    面积(mm2)N/A2.740.44~0.500.290.721.700.18
    下载: 导出CSV

    表 2  硅基毫米波功率放大器性能汇总

    文献编号[49][50][51][52][53][54][55][56][57]
    工艺45 nm
    CMOS SOI
    45 nm
    CMOS SOI
    65 nm
    CMOS
    28 nm
    UTBB
    FD-SOI
    40 nm
    CMOS
    65 nm
    CMOS
    40 nm
    CMOS
    0.13 μm
    SiGe
    BiCMOS
    45 nm
    CMOS
    SOI
    结构堆叠堆叠堆叠功率合成功率合成功率合成功率合成功率合成功率合成
    频率(GHz)41.045.060.060.060.060.070.3~85.542.060.0
    电源电压(V)5.02.72.51.01.01.00.94.0/2.42.2
    PSAT(dBm)21.618.6~19.417.618.917.417.720.928.430.1
    PAEMAX(%)25.132.0~33.920.417.728.511.122.310.020.8
    增益(dB)8.99.523.535.021.219.218.118.524.7
    面积(mm2)0.3000.3000.2400.1620.0740.8300.1905.5506.600
    下载: 导出CSV
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  • 通讯作者:  池保勇, chibylxc@tsinghua.edu.cn
  • 收稿日期:  2019-09-02
  • 录用日期:  2019-12-04
  • 网络出版日期:  2019-12-10
  • 刊出日期:  2020-01-01
通讯作者: 陈斌, bchen63@163.com
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