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面向密码算法的大位宽比特置换操作高速实现方案

戴紫彬 马超 李伟 南龙梅

戴紫彬, 马超, 李伟, 南龙梅. 面向密码算法的大位宽比特置换操作高速实现方案[J]. 电子与信息学报, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
引用本文: 戴紫彬, 马超, 李伟, 南龙梅. 面向密码算法的大位宽比特置换操作高速实现方案[J]. 电子与信息学报, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
DAI Zibin, MA Chao, LI Wei, NAN Longmei. Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms[J]. Journal of Electronics and Information Technology, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285
Citation: DAI Zibin, MA Chao, LI Wei, NAN Longmei. Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms[J]. Journal of Electronics and Information Technology, 2017, 39(9): 2119-2126. doi: 10.11999/JEIT161285

面向密码算法的大位宽比特置换操作高速实现方案

doi: 10.11999/JEIT161285
基金项目: 

国家自然科学基金(61404175)

Wide-width Bit Permutation Instructions for Accelerating Cryptographic Algorithms

Funds: 

The National Natural Science Foundation of China (61404175)

  • 摘要: 针对面向字级优化的通用处理器,在应对密码算法中大位宽比特置换操作时效率较低的问题,该文提出2N-2N和kN-kN(k2)的大位宽比特置换操作高速实现方案。并针对方案中涉及的比特提取和比特提取-移位两种操作,分别提出专用扩展指令BEX, BEX-ROT。在此基础上,对专用指令硬件架构的高效设计进行研究,提出一种基于Inverse Butterfly网络统一硬件架构-RERS(Reconfigurable Extract and Rotation Shifter)及相应可重构路由算法,以最大限度地共享硬件资源,减小电路面积。实验结果表明,所提方案能够将处理器架构执行大位宽比特置换操作的指令条数缩减约10倍,大幅提升其处理效率。同时,由专用指令所带来的硬件资源开销和延迟开销均较低,不会影响到原架构正常工作频率。
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    出版历程
    • 收稿日期:  2016-11-25
    • 修回日期:  2017-06-05
    • 刊出日期:  2017-09-19

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