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片上网络通信性能分析建模与缓存分配优化算法

王坚 李玉柏 蒋勇男

王坚, 李玉柏, 蒋勇男. 片上网络通信性能分析建模与缓存分配优化算法[J]. 电子与信息学报, 2009, 31(5): 1059-1062. doi: 10.3724/SP.J.1146.2008.00491
引用本文: 王坚, 李玉柏, 蒋勇男. 片上网络通信性能分析建模与缓存分配优化算法[J]. 电子与信息学报, 2009, 31(5): 1059-1062. doi: 10.3724/SP.J.1146.2008.00491
Wang Jian, Li Yu-bai, Jiang Yong-nan. Communication Performance Analytical Model and Buffer Allocation Optimizing Algorithm for Network-on-Chip[J]. Journal of Electronics and Information Technology, 2009, 31(5): 1059-1062. doi: 10.3724/SP.J.1146.2008.00491
Citation: Wang Jian, Li Yu-bai, Jiang Yong-nan. Communication Performance Analytical Model and Buffer Allocation Optimizing Algorithm for Network-on-Chip[J]. Journal of Electronics and Information Technology, 2009, 31(5): 1059-1062. doi: 10.3724/SP.J.1146.2008.00491

片上网络通信性能分析建模与缓存分配优化算法

doi: 10.3724/SP.J.1146.2008.00491
基金项目: 

国家自然科学基金(60575031)资助课题

Communication Performance Analytical Model and Buffer Allocation Optimizing Algorithm for Network-on-Chip

  • 摘要: 该文建立了一种面向应用设计的片上网络的性能分析模型,并在此基础上提出了片上缓存优化策略和分配算法。在硬件实现平台上的仿真表明,该文建立的片上网络分析模型能很好地分析片上网络通信时延和路由节点各方向的阻塞概率,以此进行片上网络的缓存资源优化,能在同等缓存资源的情况下降低数据通过网络的平均时延,使片上网络的性能得到改善。
  • Benini L and De Micheli G. Networks on chips: A new SoCparadigm [J]. Computer, 2002, 35(1): 70-78.[2]Murali S, Meloni P, and Angiolini F, et al.. Designingapplication-specific networks on chips with floorplaninformation [C]. ICCAD '06. IEEE/ACM InternationalConference on Computer-Aided Design, San Jose, CA, USA,Nov. 2006: 355-362.[3]Jeang Yuan-Long, Hung Chung-Wei, and ChiangChuen-Muh. A methodology based on maximal-profitspanning tree for designing application specific networks onchip [C][J].ICICIC '06. First International Conference onInnovative Computing, Information and Control, Beijing,Aug.2006, 2:18-21[4]Andreas H, Maarten W, and Arno M, et al.. Applyingdataflow analysis to dimension buffers for guaranteedperformance in networks on chip [C]. NoCS 2008. SecondACM/IEEE International Symposium on Networks-on-Chip,Newcastle University, UK, 7-10 April 2008: 211-212.[5]Hu J and Marculescu R. DyADsmart routing for networkson-chip [C]. Proc. DAC, San Diego, Jun 2004: 260-263.[6]Saastamoinen I and Alho J N M. Buffer implementation forproteo networks-on-chip [C]. Proc Int Symp Circuits andSyst, 2003: 113-116.[7]Dally W J and Towles B. Route packets, not wires: On-chipinterconnection networks [C]. Proceedings of DAC, LasVegas, Nevada, USA, June 18-22, 2001: 683-689.[8]Guerrier P and Greiner A. A generic architecture for on chippacket-switched interconnections [C]. Proceedings ofDATE,Paris, France, March 27-30, 2000: 250-256.[9]Wu Ning, Ge Fen, and Wang Qi. Simulation andperformance analysis of network on chip architectures usingOPNET [C]. ASICON '07. 7th International Conference onASIC, Guilin, China, 22-25 Oct 2007: 1285-1288.[10]Adve V S and Vernon M K. Performance analysis of meshinterconnection networks with deterministic routing [J].IEEE Trans. on Parallel Distrib. Syst.1994, 5(3):225-246[11]Dally W J. Performance analysis of k-ary n-cubeinterconnection networks [J]. Computer, 1990, 39(6):775-785.[12]Kermani P and Kleinrock L. Virtual cut-through: A newcomputer communication switching technique [J]. ComputerNetworks, 1979, 3: 267-289.[13]Kleinrock L. Queueing Systems [M]. Vol.I: Theroy. WileyInterscience, New York, 1975: 17-85.[14]Hu Jingcao, Ogras U Y, and Marculescu R. Applicationspecificbuffer space allocation for networks-on-chip routerdesign [J].IEEE Trans. on Computer-Aided Design ofIntegrated Circuits and Systems.2006, 25(12):2919-2933
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  • 被引次数: 0
出版历程
  • 收稿日期:  2008-04-24
  • 修回日期:  2008-09-29
  • 刊出日期:  2009-05-19

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