为克服多元LDPC码的扩展最小和(Extended Min-Sum, EMS)译码算法中对数似然比(Log Likelihood Ratio, LLR)生成及排序复杂度过高的问题，该文针对以BPSK为调制方式的编码调制系统，提出一种快速而简单的LLR生成算法。该算法采用一种低复杂度的迭代计算方式，可快速生成并排序LLR，适用于硬件实现的流水线结构，能够加速译码器的译码速度并提高译码器吞吐量。仿真结果表明：所提出算法对译码性能基本没有影响且极大降低LLR计算的复杂度，是一种适用于高速多元LDPC译码器前端实现的候选算法。
To overcome the drawback of the high complexity of Log Likelihood Ratio (LLR) generation and its accompanying sorting in Extended Min-Sum (EMS) decoding of non-binary Low-Density Parity-Check (LDPC) codes, for non-binary LDPC-coded BPSK modulation systems, a high-speed and low-complexity LLR derivation algorithm is proposed in this paper. The proposed algorithm employs an iterative computation method to generate and sort the LLRs. The front-end of a decoder implementing the proposed algorithm can work in pipeline mode, which accelerates the decoding process and increases the throughput of the decoder. Simulation results show that, the proposed algorithm incurs negligible performance loss, which makes it a good candidate for the hardware implementation of the front-end in non-binary LDPC decoders.