该文通过对低密度校验(LDPC)码的编译码过程进行分析，提出了一种基于FPGA的LDPC码编译码器联合设计方法，该方法使编码器和译码器共用同一校验计算电路和复用相同的RAM存储块，有效减少了硬件资源的消耗量。该方法适合于采用校验矩阵进行编码和译码的情况，不仅适用于全并行的编译码器结构，同时也适用于目前广泛采用的部分并行结构，且能够使用和积、最小和等多种译码算法。采用该方法对两组不同的LDPC码进行部分并行结构的编译码器联合设计，在Xilinx XC4VLX80 FPGA上的实现结果表明，设计得到的编码器和译码器可并行工作，且仅占用略多于单个译码器的硬件资源，提出的设计方法能够在不降低吞吐量的同时有效减少系统对硬件资源的需求。
A joint design of FPGA-based encoder and decoder of LDPC codes is proposed. In this new design, the LDPC encoder and decoder share the same parity-check calculation circuit and the same RAM block, resulting in significantly reduced resource consumption in hardware implementations. The design is suitable for encoding and decoding realizations based on parity-check matrix. It can accommodate full-parallel architectures both for the encoder and decoder, or partial-parallel architectures that are widely adopted nowadays. Furthermore, various decoding algorithms such as the sum-product and the min-sum algorithms can be adopted in this design. The proposed joint design method is applied to design the enoder and decoder of two different groups of LDPC codes, both with a partial-parallel structure. The implementation based on an Xinlinx XC4VLX80 FPGA shows that the designed encoder and decoder can work well in a parallel way, and only consumes slightly more hardware resources than that required by a single decoder. As a result, the proposed design can effectively reduce the hardward consumption without sacrificing the throughput.