该文研究准循环多进制LDPC码的构造，给出多进制LDPC码的设计流程和构造方法。详细讨论了多进制LDPC码的性能影响因素，综合考虑了环长和环的连通性对性能的影响，研究了母矩阵扩展中偏移因子的选择以及GF(q)上非零元素替代。同时提出了次优解的搜索方法，以降低搜索复杂度。最后，将提出的方法用于不同阶数下LDPC码的构造。仿真结果表明，通过新方法构造得到的多进制LDPC码与二进制码相比，在BPSK调制方式下在误帧率10-4附近有0.2 dB的性能提升；在有限域阶数与调制阶数匹配的情况下，有更大的性能提升。与相近码长，相同码率的多进制循环码相比，该文构造得到的多进制LDPC码在误帧率10-4附近有0.25 dB的性能提升。
The construction of non-binary quasi-cyclic low-density parity-check codes are investigated. Important factors that influence the performance of non-binary LDPC codes are discussed in detail. The circle length and connectivity are taken into account in the construction. The selection of shift values to extend the mother matrix and the replacement of non-zero elements over GF(q) for the parity check matrix are studied. Meanwhile, a suboptimum method with lower complexity is proposed to search for the solution according to the new formula. The method is applied to the construction of non-binary LDPC codes over different Galois fields. Simulation results show that the codes constructed by this method outperform the corresponding binary codes by 0.2 dB at FER around10-4 on the BPSK AWGN channel. The performance gap is larger when the order of the Galois field equals the order of the modulation. Compared with non-binary cycle code with the same code rate and approximate code length, the constructed non-binary LDPC code gets an improvement of 0.25 dB at FER around 10-4.