随着新型电子器件越来越多地被机载航电设备所采用，单粒子翻转(Single Event Upset, SEU)故障已经成为影响航空飞行安全的重大隐患。首先，针对由于单粒子翻转故障的随机性，该文对不同时刻发生的单粒子翻转故障引入了多时钟控制，构建了SEU故障注入测试系统。然后模拟真实情况下单粒子效应引发的多时间点故障，研究了单粒子效应对基于FPGA构成的时序电路的影响，并在线统计了被测模块的失效数据和失效率。实验结果表明，对于基于FPGA构建容错电路，采用多时钟沿三模冗余(Triple Modular Redundancy, TMR) 加固技术可比传统TMR技术提高约1.86倍的抗SEU性能；该多时钟SEU故障注入测试系统可以快速、准确、低成本地实现单粒子翻转故障测试，从而验证了SEU加固技术的有效性。
With the new electronic devices are increasingly used by airborne avionics equipment, Single Event Upset (SEU) fault has become a major hazard on aviation safety. Because of the randomness of SEU fault, the SEU fault occurs at any moments. Firstly, a multi-clock control is introduced to construct an SEU fault injection testing system. Secondly, the system simulates multi-time point of failure with real situations caused by single event upset effects. For sequential circuits constructed by SRAM-based FPGA, the influence of SEU is studied by the system and the failure data and failure rate of the undertest module is counted online. Two kinds of FPGA-based fault-tolerant circuit are tested by this system. Comparing with the traditional Triple Modular Redundancy (TMR) technology, the anti-SEU performance of the proposed multi-clock edge TMR reinforcement technology is improved about 1.86-fold. The experiment results verify that the proposed multi-clock SEU fault injection testing system is a quick, low-cost and highly accurate test for the single-event upsets fault, and demonstrate the effectiveness of the proposed SEU reinforcement technology.